1. Field of the Invention
The present invention generally relates to semiconductor Field Effect Transistor (FET) manufacture and more particularly to improving yield and reliability in semiconductor chip manufacture.
2. Background Description
Integrated Circuits (ICs) are commonly made in the well-known complementary insulated gate Field Effect Transistor (FET) technology known as CMOS. Typical high performance ICs include CMOS devices (FETs) formed in a number of stacked layers (e.g., wiring, via, gate and gate dielectric) on a surface semiconductor (silicon) layer of a Silicon On Insulator (SOI) chip or wafer. CMOS technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). In what is typically referred to as scaling, device or FET features are shrunk to shrink corresponding device minimum dimensions, including both horizontal dimensions (e.g., minimum channel length) and vertical dimensions, e.g., channel layer depth, gate dielectric thickness, junction depths and etc. Shrinking device size increases device density and improves circuit performance (both from increased device drive capability and decreased capacitive load).
With scaling, however, what had become small, insignificant and neglectable defects have become significant, to the point of causing chip failures and negatively impacting yield. Scaling has made forming electrical contacts to device source/drain regions, especially for what are known as raised source/drain devices, for example, a considerable challenge. Typically, contacts are formed after opening (smaller and smaller) contact openings or vias through an insulation layer to the device raised source/drains, e.g., using a reactive ion etch (RIE) self-aligned contact, and filling the openings with a conductive material. However, using conventional contact oxide RIE for self-aligned contacts erodes device sidewall spacers that causes gate to source/drain shorts. These shorts have caused a significant drop in chip yield.
Thus, there exists a need for improved self-aligned source/drain contact formation in semiconductor manufacturing, and more particularly; there exists a need for self-aligned source/drain contact formation that does not incur sidewall spacer loss at contact oxide while avoiding source/drain contact to device gate shorts to improve chip yield and reliability.